/**
 * *****************************************************************
 * @file    dma_ctype_map.h
 * @author  WuHao(hwu@andartechs.com.cn)
 * @version 1.0.0
 * @date    2020-11-24
 * @brief   dsp configuration registers address definition
 *
 *                 Copyright (c) 2020, Andar Technologies Inc.
 *                           www.andartechs.com 
 *
 * *****************************************************************
 */
#ifndef __DSP_MAP_H
#define __DSP_MAP_H
#include "adt3102_type_define.h"
//#define dsp_int_status 0x00
#define dsp_int_status_fft_exp_shift 0
#define dsp_int_status_fft_exp_mask ((1<<8)-1)

//#define dsp_int_clear 0x01
#define dsp_int_clear_fft_start_bit (1<<2)
#define dsp_int_clear_fft_clr1_bit (1<<1)
#define dsp_int_clear_fft_clr0_bit (1<<0)

//#define dsp_fft_ctrl 0x02
#define dsp_fft_ctrl_fft_exp_bp_bit (1<<11)
#define dsp_fft_ctrl_fft_en_bit (1<<10)
#define dsp_fft_ctrl_fft_len_shift 0
#define dsp_fft_ctrl_fft_len_mask ((1<<10)-1)

//#define dsp_fft_status 0x03
#define dsp_fft_status_fft_state_shift 0
#define dsp_fft_status_fft_state_mask ((1<<12)-1)

//#define dsp_rsv1 0x04
#define dsp_rsv1_reserve1_shift 0
#define dsp_rsv1_reserve1_mask ((1<<32)-1)

//#define dsp_rsv2 0x05
#define dsp_rsv2_reserve2_shift 0
#define dsp_rsv2_reserve2_mask ((1<<32)-1)

//#define dsp_rsv3 0x06
#define dsp_rsv3_reserve3_shift 0
#define dsp_rsv3_reserve3_mask ((1<<32)-1)

//#define dsp_rsv4 0x07
#define dsp_rsv4_reserve4_shift 0
#define dsp_rsv4_reserve4_mask ((1<<32)-1)

//#define ds_start_trig_mux 0x08

//#define ds_adc_enable 0x09
#define ds_adc_enable_adc_signed_flag_bit (1<<4)
#define ds_adc_enable_ch1_q_en_bit (1<<3)
#define ds_adc_enable_ch1_i_en_bit (1<<2)
#define ds_adc_enable_ch0_q_en_bit (1<<1)
#define ds_adc_enable_ch0_i_en_bit (1<<0)

//#define ds_adc_data_ch0_offset 0x0a
#define ds_adc_data_ch0_offset_ch0_q_offset_shift 11
#define ds_adc_data_ch0_offset_ch0_q_offset_mask ((1<<11)-1)
#define ds_adc_data_ch0_offset_ch0_i_offset_shift 0
#define ds_adc_data_ch0_offset_ch0_i_offset_mask ((1<<11)-1)

//#define ds_adc_data_ch1_offset 0x0b
#define ds_adc_data_ch1_offset_ch1_q_offset_shift 11
#define ds_adc_data_ch1_offset_ch1_q_offset_mask ((1<<11)-1)
#define ds_adc_data_ch1_offset_ch1_i_offset_shift 0
#define ds_adc_data_ch1_offset_ch1_i_offset_mask ((1<<11)-1)

//#define ds_adc_format_ctrl 0x0c
#define ds_adc_format_ctrl_ch_swap_bit (1<<7)
#define ds_adc_format_ctrl_offset_auto_bit (1<<6)
#define ds_adc_format_ctrl_iq_swap_shift 4
#define ds_adc_format_ctrl_iq_swap_mask ((1<<2)-1)
#define ds_adc_format_ctrl_dat_invt_shift 0
#define ds_adc_format_ctrl_dat_invt_mask ((1<<4)-1)

//#define wn_wn_para 0x0d
#define wn_wn_para_wn_len_shift 2
#define wn_wn_para_wn_len_mask ((1<<10)-1)
#define wn_wn_para_bypass_bit (1<<1)
#define wn_wn_para_cof_sel_bit (1<<0)

//#define ds_adc_dma_src_select 0x0e
#define ds_adc_dma_src_select_dma_err_intr_en_bit (1<<3)
#define ds_adc_dma_src_select_adc_dma_select_shift 0
#define ds_adc_dma_src_select_adc_dma_select_mask ((1<<3)-1)

//#define ds_adc_dma_err_code 0x0f
#define ds_adc_dma_err_code_adc_rx_ch1_full_bit (1<<7)
#define ds_adc_dma_err_code_adc_rx_ch0_full_bit (1<<6)
#define ds_adc_dma_err_code_adc_rx_ch1_empty_bit (1<<5)
#define ds_adc_dma_err_code_adc_rx_ch0_empty_bit (1<<4)
#define ds_adc_dma_err_code_adc_dma_ch1_empty_bit (1<<3)
#define ds_adc_dma_err_code_adc_dma_ch0_empty_bit (1<<2)
#define ds_adc_dma_err_code_adc_dma_ch1_full_bit (1<<1)
#define ds_adc_dma_err_code_adc_dma_ch0_full_bit (1<<0)

//#define dsp_fifo_full_clear 0x10
#define dsp_fifo_full_clear_adc_fifo_full_clear_bit (1<<1)
#define dsp_fifo_full_clear_dma_fifo_full_clear_bit (1<<0)

//#define dma_full_intr_clear 0x11

//#define ds_start 0x12
#define ds_start_adc_reserve_bit (1<<1)
#define ds_start_adc_start_bit (1<<0)

//#define ds_ctrl 0x13
#define ds_ctrl_adc_rf_bist_bit (1<<2)
#define ds_ctrl_adc_ctrl_reserve_bit (1<<1)
#define ds_ctrl_adc_ctrl_mode_bit (1<<0)

//#define ds_ds_interval_num 0x14
#define ds_ds_interval_num_interval_num_shift 0
#define ds_ds_interval_num_interval_num_mask ((1<<16)-1)

//#define ds_ds_start_num 0x15
#define ds_ds_start_num_start_num_shift 0
#define ds_ds_start_num_start_num_mask ((1<<16)-1)

//#define ds_ds_adc_valid_num 0x16
#define ds_ds_adc_valid_num_adc_valid_num_shift 0
#define ds_ds_adc_valid_num_adc_valid_num_mask ((1<<16)-1)

//#define ds_ds_scan_num 0x17
#define ds_ds_scan_num_scan_num_shift 0
#define ds_ds_scan_num_scan_num_mask ((1<<8)-1)

//#define ds_ds_pulse_num 0x18
#define ds_ds_pulse_num_pulse_num_shift 0
#define ds_ds_pulse_num_pulse_num_mask ((1<<16)-1)

//#define fir_grp_dly_select 0x19
#define fir_grp_dly_select_din_dly2_en_bit (1<<7)
#define fir_grp_dly_select_grp_dly_en_bit (1<<6)
#define fir_grp_dly_select_grp_dly_num_shift 0
#define fir_grp_dly_select_grp_dly_num_mask ((1<<6)-1)

//#define fir_reg0 0x1a
#define fir_reg0_cof1_shift 13
#define fir_reg0_cof1_mask ((1<<13)-1)
#define fir_reg0_cof0_shift 0
#define fir_reg0_cof0_mask ((1<<13)-1)

//#define fir_reg1 0x1b
#define fir_reg1_cof3_shift 13
#define fir_reg1_cof3_mask ((1<<13)-1)
#define fir_reg1_cof2_shift 0
#define fir_reg1_cof2_mask ((1<<13)-1)

//#define fir_reg2 0x1c
#define fir_reg2_cof5_shift 13
#define fir_reg2_cof5_mask ((1<<13)-1)
#define fir_reg2_cof4_shift 0
#define fir_reg2_cof4_mask ((1<<13)-1)

//#define fir_reg3 0x1d
#define fir_reg3_cof7_shift 13
#define fir_reg3_cof7_mask ((1<<13)-1)
#define fir_reg3_cof6_shift 0
#define fir_reg3_cof6_mask ((1<<13)-1)

//#define fir_reg4 0x1e
#define fir_reg4_cof9_shift 13
#define fir_reg4_cof9_mask ((1<<13)-1)
#define fir_reg4_cof8_shift 0
#define fir_reg4_cof8_mask ((1<<13)-1)

//#define fir_reg5 0x1f
#define fir_reg5_cof11_shift 13
#define fir_reg5_cof11_mask ((1<<13)-1)
#define fir_reg5_cof10_shift 0
#define fir_reg5_cof10_mask ((1<<13)-1)

//#define fir_reg6 0x20
#define fir_reg6_cof13_shift 13
#define fir_reg6_cof13_mask ((1<<13)-1)
#define fir_reg6_cof12_shift 0
#define fir_reg6_cof12_mask ((1<<13)-1)

//#define fir_reg7 0x21
#define fir_reg7_cof15_shift 13
#define fir_reg7_cof15_mask ((1<<13)-1)
#define fir_reg7_cof14_shift 0
#define fir_reg7_cof14_mask ((1<<13)-1)

//#define fir_reg8 0x22
#define fir_reg8_cof17_shift 13
#define fir_reg8_cof17_mask ((1<<13)-1)
#define fir_reg8_cof16_shift 0
#define fir_reg8_cof16_mask ((1<<13)-1)

//#define fir_reg9 0x23
#define fir_reg9_cof19_shift 13
#define fir_reg9_cof19_mask ((1<<13)-1)
#define fir_reg9_cof18_shift 0
#define fir_reg9_cof18_mask ((1<<13)-1)

//#define fir_reg10 0x24
#define fir_reg10_cof21_shift 13
#define fir_reg10_cof21_mask ((1<<13)-1)
#define fir_reg10_cof20_shift 0
#define fir_reg10_cof20_mask ((1<<13)-1)

//#define fir_reg11 0x25
#define fir_reg11_cof23_shift 13
#define fir_reg11_cof23_mask ((1<<13)-1)
#define fir_reg11_cof22_shift 0
#define fir_reg11_cof22_mask ((1<<13)-1)

//#define fir_reg12 0x26
#define fir_reg12_cof25_shift 13
#define fir_reg12_cof25_mask ((1<<13)-1)
#define fir_reg12_cof24_shift 0
#define fir_reg12_cof24_mask ((1<<13)-1)

//#define fir_reg13 0x27
#define fir_reg13_cof27_shift 13
#define fir_reg13_cof27_mask ((1<<13)-1)
#define fir_reg13_cof26_shift 0
#define fir_reg13_cof26_mask ((1<<13)-1)

//#define fir_reg14 0x28
#define fir_reg14_cof29_shift 13
#define fir_reg14_cof29_mask ((1<<13)-1)
#define fir_reg14_cof28_shift 0
#define fir_reg14_cof28_mask ((1<<13)-1)

//#define fir_reg15 0x29
#define fir_reg15_cof31_shift 13
#define fir_reg15_cof31_mask ((1<<13)-1)
#define fir_reg15_cof30_shift 0
#define fir_reg15_cof30_mask ((1<<13)-1)

//#define fir_cof_sample_rate 0x2a
#define fir_cof_sample_rate_bypass_bit (1<<17)
#define fir_cof_sample_rate_down_sample_rate_shift 13
#define fir_cof_sample_rate_down_sample_rate_mask ((1<<4)-1)
#define fir_cof_sample_rate_cof32_shift 0
#define fir_cof_sample_rate_cof32_mask ((1<<13)-1)

//#define agc_ctrl1 0x2b
#define agc_ctrl1_bypass_bit (1<<19)
#define agc_ctrl1_ch_sel_shift 17
#define agc_ctrl1_ch_sel_mask ((1<<2)-1)
#define agc_ctrl1_samp_sel_shift 14
#define agc_ctrl1_samp_sel_mask ((1<<3)-1)
#define agc_ctrl1_tbl_max_shift 8
#define agc_ctrl1_tbl_max_mask ((1<<6)-1)
#define agc_ctrl1_frc_hld_bit (1<<7)
#define agc_ctrl1_cpu_gain_en_bit (1<<6)
#define agc_ctrl1_cpu_gain_shift 0
#define agc_ctrl1_cpu_gain_mask ((1<<6)-1)

//#define agc_ctrl2 0x2c
#define agc_ctrl2_adj_num_shift 24
#define agc_ctrl2_adj_num_mask ((1<<8)-1)
#define agc_ctrl2_vga_dly_shift 12
#define agc_ctrl2_vga_dly_mask ((1<<9)-1)
#define agc_ctrl2_init_dly_shift 0
#define agc_ctrl2_init_dly_mask ((1<<9)-1)

//#define agc_threshold0 0x2d
#define agc_threshold0_max0_shift 12
#define agc_threshold0_max0_mask ((1<<9)-1)
#define agc_threshold0_min0_shift 0
#define agc_threshold0_min0_mask ((1<<9)-1)

//#define agc_threshold1 0x2e
#define agc_threshold1_max1_shift 12
#define agc_threshold1_max1_mask ((1<<9)-1)
#define agc_threshold1_min1_shift 0
#define agc_threshold1_min1_mask ((1<<9)-1)

//#define agc_stat0 0x2f
#define agc_stat0_adj_num0_shift 16
#define agc_stat0_adj_num0_mask ((1<<8)-1)
#define agc_stat0_agc_lock0_bit (1<<15)
#define agc_stat0_gain_idx0_shift 9
#define agc_stat0_gain_idx0_mask ((1<<6)-1)
#define agc_stat0_avg_pwr0_shift 0
#define agc_stat0_avg_pwr0_mask ((1<<9)-1)

//#define agc_stat1 0x30
#define agc_stat1_adj_num1_shift 16
#define agc_stat1_adj_num1_mask ((1<<8)-1)
#define agc_stat1_agc_lock1_bit (1<<15)
#define agc_stat1_gain_idx1_shift 9
#define agc_stat1_gain_idx1_mask ((1<<6)-1)
#define agc_stat1_avg_pwr1_shift 0
#define agc_stat1_avg_pwr1_mask ((1<<9)-1)

//#define agc_sqr_max0 0x31
#define agc_sqr_max0_ovf_q0_bit (1<<19)
#define agc_sqr_max0_ovf_i0_bit (1<<18)
#define agc_sqr_max0_sqr_max_q0_shift 9
#define agc_sqr_max0_sqr_max_q0_mask ((1<<9)-1)
#define agc_sqr_max0_sqr_max_i0_shift 0
#define agc_sqr_max0_sqr_max_i0_mask ((1<<9)-1)

//#define agc_sqr_max1 0x32
#define agc_sqr_max1_ovf_q1_bit (1<<19)
#define agc_sqr_max1_ovf_i1_bit (1<<18)
#define agc_sqr_max1_sqr_max_q1_shift 9
#define agc_sqr_max1_sqr_max_q1_mask ((1<<9)-1)
#define agc_sqr_max1_sqr_max_i1_shift 0
#define agc_sqr_max1_sqr_max_i1_mask ((1<<9)-1)

//#define agc_dc0 0x33
#define agc_dc0_dc_q_ch0_shift 11
#define agc_dc0_dc_q_ch0_mask ((1<<11)-1)
#define agc_dc0_dc_i_ch0_shift 0
#define agc_dc0_dc_i_ch0_mask ((1<<11)-1)

//#define agc_dc1 0x34
#define agc_dc1_dc_q_ch1_shift 11
#define agc_dc1_dc_q_ch1_mask ((1<<11)-1)
#define agc_dc1_dc_i_ch1_shift 0
#define agc_dc1_dc_i_ch1_mask ((1<<11)-1)

//#define cfar_str 0x35

//#define cfar_dat_number 0x36
#define cfar_dat_number_acc_sum_frz_bit (1<<8)
#define cfar_dat_number_dat_num_shift 0
#define cfar_dat_number_dat_num_mask ((1<<7)-1)

//#define cfar_mask0 0x37
#define cfar_mask0_msk0_shift 0
#define cfar_mask0_msk0_mask ((1<<32)-1)

//#define cfar_mask1 0x38
#define cfar_mask1_msk1_shift 0
#define cfar_mask1_msk1_mask ((1<<32)-1)

//#define cfar_done 0x39
#define cfar_done_ord_done_bit (1<<1)
#define cfar_done_acc_done_bit (1<<0)

//#define cfar_acc_sum_h 0x3a
#define cfar_acc_sum_h_acc_sum_hi_shift 0
#define cfar_acc_sum_h_acc_sum_hi_mask ((1<<6)-1)

//#define cfar_acc_sum_l 0x3b
#define cfar_acc_sum_l_acc_sum_lo_shift 0
#define cfar_acc_sum_l_acc_sum_lo_mask ((1<<32)-1)

//#define cfar_ord_idx 0x3c
#define cfar_ord_idx_ord_index_shift 0
#define cfar_ord_idx_ord_index_mask ((1<<6)-1)

//#define cfar_ord_value 0x3d
#define cfar_ord_value_ord_val_shift 0
#define cfar_ord_value_ord_val_mask ((1<<32)-1)

//#define siggen_step 0x3e
#define siggen_step_stp_shift 16
#define siggen_step_stp_mask ((1<<16)-1)
#define siggen_step_chg_stp_shift 0
#define siggen_step_chg_stp_mask ((1<<16)-1)

//#define siggen_ctrl 0x3f
#define siggen_ctrl_comp_bit (1<<17)
#define siggen_ctrl_en_bit (1<<16)
#define siggen_ctrl_ang_shift 0
#define siggen_ctrl_ang_mask ((1<<16)-1)

//#define agc_gain_tb_ch0_0 0x40
#define agc_gain_tb_ch0_0_gain_tb0_0_shift 0
#define agc_gain_tb_ch0_0_gain_tb0_0_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_1 0x41
#define agc_gain_tb_ch0_1_gain_tb0_1_shift 0
#define agc_gain_tb_ch0_1_gain_tb0_1_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_2 0x42
#define agc_gain_tb_ch0_2_gain_tb0_2_shift 0
#define agc_gain_tb_ch0_2_gain_tb0_2_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_3 0x43
#define agc_gain_tb_ch0_3_gain_tb0_3_shift 0
#define agc_gain_tb_ch0_3_gain_tb0_3_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_4 0x44
#define agc_gain_tb_ch0_4_gain_tb0_4_shift 0
#define agc_gain_tb_ch0_4_gain_tb0_4_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_5 0x45
#define agc_gain_tb_ch0_5_gain_tb0_5_shift 0
#define agc_gain_tb_ch0_5_gain_tb0_5_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_6 0x46
#define agc_gain_tb_ch0_6_gain_tb0_6_shift 0
#define agc_gain_tb_ch0_6_gain_tb0_6_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_7 0x47
#define agc_gain_tb_ch0_7_gain_tb0_7_shift 0
#define agc_gain_tb_ch0_7_gain_tb0_7_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_8 0x48
#define agc_gain_tb_ch0_8_gain_tb0_8_shift 0
#define agc_gain_tb_ch0_8_gain_tb0_8_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_9 0x49
#define agc_gain_tb_ch0_9_gain_tb0_9_shift 0
#define agc_gain_tb_ch0_9_gain_tb0_9_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_10 0x4a
#define agc_gain_tb_ch0_10_gain_tb0_10_shift 0
#define agc_gain_tb_ch0_10_gain_tb0_10_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_11 0x4b
#define agc_gain_tb_ch0_11_gain_tb0_11_shift 0
#define agc_gain_tb_ch0_11_gain_tb0_11_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_12 0x4c
#define agc_gain_tb_ch0_12_gain_tb0_12_shift 0
#define agc_gain_tb_ch0_12_gain_tb0_12_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_13 0x4d
#define agc_gain_tb_ch0_13_gain_tb0_13_shift 0
#define agc_gain_tb_ch0_13_gain_tb0_13_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_14 0x4e
#define agc_gain_tb_ch0_14_gain_tb0_14_shift 0
#define agc_gain_tb_ch0_14_gain_tb0_14_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_15 0x4f
#define agc_gain_tb_ch0_15_gain_tb0_15_shift 0
#define agc_gain_tb_ch0_15_gain_tb0_15_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_16 0x50
#define agc_gain_tb_ch0_16_gain_tb0_16_shift 0
#define agc_gain_tb_ch0_16_gain_tb0_16_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_17 0x51
#define agc_gain_tb_ch0_17_gain_tb0_17_shift 0
#define agc_gain_tb_ch0_17_gain_tb0_17_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_18 0x52
#define agc_gain_tb_ch0_18_gain_tb0_18_shift 0
#define agc_gain_tb_ch0_18_gain_tb0_18_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_19 0x53
#define agc_gain_tb_ch0_19_gain_tb0_19_shift 0
#define agc_gain_tb_ch0_19_gain_tb0_19_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_20 0x54
#define agc_gain_tb_ch0_20_gain_tb0_20_shift 0
#define agc_gain_tb_ch0_20_gain_tb0_20_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_21 0x55
#define agc_gain_tb_ch0_21_gain_tb0_21_shift 0
#define agc_gain_tb_ch0_21_gain_tb0_21_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_22 0x56
#define agc_gain_tb_ch0_22_gain_tb0_22_shift 0
#define agc_gain_tb_ch0_22_gain_tb0_22_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_23 0x57
#define agc_gain_tb_ch0_23_gain_tb0_23_shift 0
#define agc_gain_tb_ch0_23_gain_tb0_23_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_24 0x58
#define agc_gain_tb_ch0_24_gain_tb0_24_shift 0
#define agc_gain_tb_ch0_24_gain_tb0_24_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_25 0x59
#define agc_gain_tb_ch0_25_gain_tb0_25_shift 0
#define agc_gain_tb_ch0_25_gain_tb0_25_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_26 0x5a
#define agc_gain_tb_ch0_26_gain_tb0_26_shift 0
#define agc_gain_tb_ch0_26_gain_tb0_26_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_27 0x5b
#define agc_gain_tb_ch0_27_gain_tb0_27_shift 0
#define agc_gain_tb_ch0_27_gain_tb0_27_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_28 0x5c
#define agc_gain_tb_ch0_28_gain_tb0_28_shift 0
#define agc_gain_tb_ch0_28_gain_tb0_28_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_29 0x5d
#define agc_gain_tb_ch0_29_gain_tb0_29_shift 0
#define agc_gain_tb_ch0_29_gain_tb0_29_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_30 0x5e
#define agc_gain_tb_ch0_30_gain_tb0_30_shift 0
#define agc_gain_tb_ch0_30_gain_tb0_30_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_31 0x5f
#define agc_gain_tb_ch0_31_gain_tb0_31_shift 0
#define agc_gain_tb_ch0_31_gain_tb0_31_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_32 0x60
#define agc_gain_tb_ch0_32_gain_tb0_32_shift 0
#define agc_gain_tb_ch0_32_gain_tb0_32_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_33 0x61
#define agc_gain_tb_ch0_33_gain_tb0_33_shift 0
#define agc_gain_tb_ch0_33_gain_tb0_33_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_34 0x62
#define agc_gain_tb_ch0_34_gain_tb0_34_shift 0
#define agc_gain_tb_ch0_34_gain_tb0_34_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_35 0x63
#define agc_gain_tb_ch0_35_gain_tb0_35_shift 0
#define agc_gain_tb_ch0_35_gain_tb0_35_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_36 0x64
#define agc_gain_tb_ch0_36_gain_tb0_36_shift 0
#define agc_gain_tb_ch0_36_gain_tb0_36_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_37 0x65
#define agc_gain_tb_ch0_37_gain_tb0_37_shift 0
#define agc_gain_tb_ch0_37_gain_tb0_37_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_38 0x66
#define agc_gain_tb_ch0_38_gain_tb0_38_shift 0
#define agc_gain_tb_ch0_38_gain_tb0_38_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_39 0x67
#define agc_gain_tb_ch0_39_gain_tb0_39_shift 0
#define agc_gain_tb_ch0_39_gain_tb0_39_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_40 0x68
#define agc_gain_tb_ch0_40_gain_tb0_40_shift 0
#define agc_gain_tb_ch0_40_gain_tb0_40_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_41 0x69
#define agc_gain_tb_ch0_41_gain_tb0_41_shift 0
#define agc_gain_tb_ch0_41_gain_tb0_41_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_42 0x6a
#define agc_gain_tb_ch0_42_gain_tb0_42_shift 0
#define agc_gain_tb_ch0_42_gain_tb0_42_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_43 0x6b
#define agc_gain_tb_ch0_43_gain_tb0_43_shift 0
#define agc_gain_tb_ch0_43_gain_tb0_43_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_44 0x6c
#define agc_gain_tb_ch0_44_gain_tb0_44_shift 0
#define agc_gain_tb_ch0_44_gain_tb0_44_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_45 0x6d
#define agc_gain_tb_ch0_45_gain_tb0_45_shift 0
#define agc_gain_tb_ch0_45_gain_tb0_45_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_46 0x6e
#define agc_gain_tb_ch0_46_gain_tb0_46_shift 0
#define agc_gain_tb_ch0_46_gain_tb0_46_mask ((1<<17)-1)

//#define agc_gain_tb_ch0_47 0x6f
#define agc_gain_tb_ch0_47_gain_tb0_47_shift 0
#define agc_gain_tb_ch0_47_gain_tb0_47_mask ((1<<17)-1)

//#define agc_lna_gain_tb_ch0_0 0x70
#define agc_lna_gain_tb_ch0_0_lna_gain_tb0_0_shift 0
#define agc_lna_gain_tb_ch0_0_lna_gain_tb0_0_mask ((1<<13)-1)

//#define agc_lna_gain_tb_ch0_1 0x71
#define agc_lna_gain_tb_ch0_1_lna_gain_tb0_1_shift 0
#define agc_lna_gain_tb_ch0_1_lna_gain_tb0_1_mask ((1<<13)-1)

//#define agc_lna_gain_tb_ch0_2 0x72
#define agc_lna_gain_tb_ch0_2_lna_gain_tb0_2_shift 0
#define agc_lna_gain_tb_ch0_2_lna_gain_tb0_2_mask ((1<<13)-1)

//#define agc_lna_gain_tb_ch0_3 0x73
#define agc_lna_gain_tb_ch0_3_lna_gain_tb0_3_shift 0
#define agc_lna_gain_tb_ch0_3_lna_gain_tb0_3_mask ((1<<13)-1)

//#define agc_lna_gain_tb_ch0_4 0x74
#define agc_lna_gain_tb_ch0_4_lna_gain_tb0_4_shift 0
#define agc_lna_gain_tb_ch0_4_lna_gain_tb0_4_mask ((1<<13)-1)

//#define agc_lna_gain_tb_ch0_5 0x75
#define agc_lna_gain_tb_ch0_5_lna_gain_tb0_5_shift 0
#define agc_lna_gain_tb_ch0_5_lna_gain_tb0_5_mask ((1<<13)-1)

//#define agc_lna_gain_tb_ch0_6 0x76
#define agc_lna_gain_tb_ch0_6_lna_gain_tb0_6_shift 0
#define agc_lna_gain_tb_ch0_6_lna_gain_tb0_6_mask ((1<<13)-1)

//#define agc_lna_gain_tb_ch0_7 0x77
#define agc_lna_gain_tb_ch0_7_lna_gain_tb0_7_shift 0
#define agc_lna_gain_tb_ch0_7_lna_gain_tb0_7_mask ((1<<13)-1)

//#define agc_gain_tb_ch1_0 0x78
#define agc_gain_tb_ch1_0_gain_tb1_0_shift 0
#define agc_gain_tb_ch1_0_gain_tb1_0_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_1 0x79
#define agc_gain_tb_ch1_1_gain_tb1_1_shift 0
#define agc_gain_tb_ch1_1_gain_tb1_1_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_2 0x7a
#define agc_gain_tb_ch1_2_gain_tb1_2_shift 0
#define agc_gain_tb_ch1_2_gain_tb1_2_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_3 0x7b
#define agc_gain_tb_ch1_3_gain_tb1_3_shift 0
#define agc_gain_tb_ch1_3_gain_tb1_3_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_4 0x7c
#define agc_gain_tb_ch1_4_gain_tb1_4_shift 0
#define agc_gain_tb_ch1_4_gain_tb1_4_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_5 0x7d
#define agc_gain_tb_ch1_5_gain_tb1_5_shift 0
#define agc_gain_tb_ch1_5_gain_tb1_5_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_6 0x7e
#define agc_gain_tb_ch1_6_gain_tb1_6_shift 0
#define agc_gain_tb_ch1_6_gain_tb1_6_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_7 0x7f
#define agc_gain_tb_ch1_7_gain_tb1_7_shift 0
#define agc_gain_tb_ch1_7_gain_tb1_7_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_8 0x80
#define agc_gain_tb_ch1_8_gain_tb1_8_shift 0
#define agc_gain_tb_ch1_8_gain_tb1_8_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_9 0x81
#define agc_gain_tb_ch1_9_gain_tb1_9_shift 0
#define agc_gain_tb_ch1_9_gain_tb1_9_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_10 0x82
#define agc_gain_tb_ch1_10_gain_tb1_10_shift 0
#define agc_gain_tb_ch1_10_gain_tb1_10_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_11 0x83
#define agc_gain_tb_ch1_11_gain_tb1_11_shift 0
#define agc_gain_tb_ch1_11_gain_tb1_11_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_12 0x84
#define agc_gain_tb_ch1_12_gain_tb1_12_shift 0
#define agc_gain_tb_ch1_12_gain_tb1_12_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_13 0x85
#define agc_gain_tb_ch1_13_gain_tb1_13_shift 0
#define agc_gain_tb_ch1_13_gain_tb1_13_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_14 0x86
#define agc_gain_tb_ch1_14_gain_tb1_14_shift 0
#define agc_gain_tb_ch1_14_gain_tb1_14_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_15 0x87
#define agc_gain_tb_ch1_15_gain_tb1_15_shift 0
#define agc_gain_tb_ch1_15_gain_tb1_15_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_16 0x88
#define agc_gain_tb_ch1_16_gain_tb1_16_shift 0
#define agc_gain_tb_ch1_16_gain_tb1_16_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_17 0x89
#define agc_gain_tb_ch1_17_gain_tb1_17_shift 0
#define agc_gain_tb_ch1_17_gain_tb1_17_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_18 0x8a
#define agc_gain_tb_ch1_18_gain_tb1_18_shift 0
#define agc_gain_tb_ch1_18_gain_tb1_18_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_19 0x8b
#define agc_gain_tb_ch1_19_gain_tb1_19_shift 0
#define agc_gain_tb_ch1_19_gain_tb1_19_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_20 0x8c
#define agc_gain_tb_ch1_20_gain_tb1_20_shift 0
#define agc_gain_tb_ch1_20_gain_tb1_20_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_21 0x8d
#define agc_gain_tb_ch1_21_gain_tb1_21_shift 0
#define agc_gain_tb_ch1_21_gain_tb1_21_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_22 0x8e
#define agc_gain_tb_ch1_22_gain_tb1_22_shift 0
#define agc_gain_tb_ch1_22_gain_tb1_22_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_23 0x8f
#define agc_gain_tb_ch1_23_gain_tb1_23_shift 0
#define agc_gain_tb_ch1_23_gain_tb1_23_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_24 0x90
#define agc_gain_tb_ch1_24_gain_tb1_24_shift 0
#define agc_gain_tb_ch1_24_gain_tb1_24_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_25 0x91
#define agc_gain_tb_ch1_25_gain_tb1_25_shift 0
#define agc_gain_tb_ch1_25_gain_tb1_25_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_26 0x92
#define agc_gain_tb_ch1_26_gain_tb1_26_shift 0
#define agc_gain_tb_ch1_26_gain_tb1_26_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_27 0x93
#define agc_gain_tb_ch1_27_gain_tb1_27_shift 0
#define agc_gain_tb_ch1_27_gain_tb1_27_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_28 0x94
#define agc_gain_tb_ch1_28_gain_tb1_28_shift 0
#define agc_gain_tb_ch1_28_gain_tb1_28_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_29 0x95
#define agc_gain_tb_ch1_29_gain_tb1_29_shift 0
#define agc_gain_tb_ch1_29_gain_tb1_29_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_30 0x96
#define agc_gain_tb_ch1_30_gain_tb1_30_shift 0
#define agc_gain_tb_ch1_30_gain_tb1_30_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_31 0x97
#define agc_gain_tb_ch1_31_gain_tb1_31_shift 0
#define agc_gain_tb_ch1_31_gain_tb1_31_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_32 0x98
#define agc_gain_tb_ch1_32_gain_tb1_32_shift 0
#define agc_gain_tb_ch1_32_gain_tb1_32_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_33 0x99
#define agc_gain_tb_ch1_33_gain_tb1_33_shift 0
#define agc_gain_tb_ch1_33_gain_tb1_33_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_34 0x9a
#define agc_gain_tb_ch1_34_gain_tb1_34_shift 0
#define agc_gain_tb_ch1_34_gain_tb1_34_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_35 0x9b
#define agc_gain_tb_ch1_35_gain_tb1_35_shift 0
#define agc_gain_tb_ch1_35_gain_tb1_35_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_36 0x9c
#define agc_gain_tb_ch1_36_gain_tb1_36_shift 0
#define agc_gain_tb_ch1_36_gain_tb1_36_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_37 0x9d
#define agc_gain_tb_ch1_37_gain_tb1_37_shift 0
#define agc_gain_tb_ch1_37_gain_tb1_37_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_38 0x9e
#define agc_gain_tb_ch1_38_gain_tb1_38_shift 0
#define agc_gain_tb_ch1_38_gain_tb1_38_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_39 0x9f
#define agc_gain_tb_ch1_39_gain_tb1_39_shift 0
#define agc_gain_tb_ch1_39_gain_tb1_39_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_40 0xa0
#define agc_gain_tb_ch1_40_gain_tb1_40_shift 0
#define agc_gain_tb_ch1_40_gain_tb1_40_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_41 0xa1
#define agc_gain_tb_ch1_41_gain_tb1_41_shift 0
#define agc_gain_tb_ch1_41_gain_tb1_41_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_42 0xa2
#define agc_gain_tb_ch1_42_gain_tb1_42_shift 0
#define agc_gain_tb_ch1_42_gain_tb1_42_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_43 0xa3
#define agc_gain_tb_ch1_43_gain_tb1_43_shift 0
#define agc_gain_tb_ch1_43_gain_tb1_43_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_44 0xa4
#define agc_gain_tb_ch1_44_gain_tb1_44_shift 0
#define agc_gain_tb_ch1_44_gain_tb1_44_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_45 0xa5
#define agc_gain_tb_ch1_45_gain_tb1_45_shift 0
#define agc_gain_tb_ch1_45_gain_tb1_45_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_46 0xa6
#define agc_gain_tb_ch1_46_gain_tb1_46_shift 0
#define agc_gain_tb_ch1_46_gain_tb1_46_mask ((1<<17)-1)

//#define agc_gain_tb_ch1_47 0xa7
#define agc_gain_tb_ch1_47_gain_tb1_47_shift 0
#define agc_gain_tb_ch1_47_gain_tb1_47_mask ((1<<17)-1)

//#define agc_lna_gain_tb_ch1_0 0xa8
#define agc_lna_gain_tb_ch1_0_lna_gain_tb1_0_shift 0
#define agc_lna_gain_tb_ch1_0_lna_gain_tb1_0_mask ((1<<13)-1)

//#define agc_lna_gain_tb_ch1_1 0xa9
#define agc_lna_gain_tb_ch1_1_lna_gain_tb1_1_shift 0
#define agc_lna_gain_tb_ch1_1_lna_gain_tb1_1_mask ((1<<13)-1)

//#define agc_lna_gain_tb_ch1_2 0xaa
#define agc_lna_gain_tb_ch1_2_lna_gain_tb1_2_shift 0
#define agc_lna_gain_tb_ch1_2_lna_gain_tb1_2_mask ((1<<13)-1)

//#define agc_lna_gain_tb_ch1_3 0xab
#define agc_lna_gain_tb_ch1_3_lna_gain_tb1_3_shift 0
#define agc_lna_gain_tb_ch1_3_lna_gain_tb1_3_mask ((1<<13)-1)

//#define agc_lna_gain_tb_ch1_4 0xac
#define agc_lna_gain_tb_ch1_4_lna_gain_tb1_4_shift 0
#define agc_lna_gain_tb_ch1_4_lna_gain_tb1_4_mask ((1<<13)-1)

//#define agc_lna_gain_tb_ch1_5 0xad
#define agc_lna_gain_tb_ch1_5_lna_gain_tb1_5_shift 0
#define agc_lna_gain_tb_ch1_5_lna_gain_tb1_5_mask ((1<<13)-1)

//#define agc_lna_gain_tb_ch1_6 0xae
#define agc_lna_gain_tb_ch1_6_lna_gain_tb1_6_shift 0
#define agc_lna_gain_tb_ch1_6_lna_gain_tb1_6_mask ((1<<13)-1)

//#define agc_lna_gain_tb_ch1_7 0xaf
#define agc_lna_gain_tb_ch1_7_lna_gain_tb1_7_shift 0
#define agc_lna_gain_tb_ch1_7_lna_gain_tb1_7_mask ((1<<13)-1)

// DSP 
typedef struct
{
  __IO uint32 dsp_int_status ;
  __IO uint32 dsp_int_clear ;
  __IO uint32 dsp_fft_ctrl ;
  __IO uint32 dsp_fft_status ;
  __IO uint32 dsp_rsv1 ;
  __IO uint32 dsp_rsv2 ;
  __IO uint32 dsp_rsv3 ;
  __IO uint32 dsp_rsv4 ;
  __IO uint32 ds_start_trig_mux ;
  __IO uint32 ds_adc_enable ;
  __IO uint32 ds_adc_data_ch0_offset ;
  __IO uint32 ds_adc_data_ch1_offset ;
  __IO uint32 ds_adc_format_ctrl ;
  __IO uint32 wn_wn_para ;
  __IO uint32 ds_adc_dma_src_select ;
  __IO uint32 ds_adc_dma_err_code ;
  __IO uint32 dsp_fifo_full_clear ;
  __IO uint32 dma_full_intr_clear ;
  __IO uint32 ds_start ;
  __IO uint32 ds_ctrl ;
  __IO uint32 ds_ds_interval_num ;
  __IO uint32 ds_ds_start_num ;
  __IO uint32 ds_ds_adc_valid_num ;
  __IO uint32 ds_ds_scan_num ;
  __IO uint32 ds_ds_pulse_num ;
  __IO uint32 fir_grp_dly_select ;
  __IO uint32 fir_reg0 ;
  __IO uint32 fir_reg1 ;
  __IO uint32 fir_reg2 ;
  __IO uint32 fir_reg3 ;
  __IO uint32 fir_reg4 ;
  __IO uint32 fir_reg5 ;
  __IO uint32 fir_reg6 ;
  __IO uint32 fir_reg7 ;
  __IO uint32 fir_reg8 ;
  __IO uint32 fir_reg9 ;
  __IO uint32 fir_reg10 ;
  __IO uint32 fir_reg11 ;
  __IO uint32 fir_reg12 ;
  __IO uint32 fir_reg13 ;
  __IO uint32 fir_reg14 ;
  __IO uint32 fir_reg15 ;
  __IO uint32 fir_cof_sample_rate ;
  __IO uint32 agc_ctrl1 ;
  __IO uint32 agc_ctrl2 ;
  __IO uint32 agc_threshold0 ;
  __IO uint32 agc_threshold1 ;
  __IO uint32 agc_stat0 ;
  __IO uint32 agc_stat1 ;
  __IO uint32 agc_sqr_max0 ;
  __IO uint32 agc_sqr_max1 ;
  __IO uint32 agc_dc0 ;
  __IO uint32 agc_dc1 ;
  __IO uint32 cfar_str ;
  __IO uint32 cfar_dat_number ;
  __IO uint32 cfar_mask0 ;
  __IO uint32 cfar_mask1 ;
  __IO uint32 cfar_done ;
  __IO uint32 cfar_acc_sum_h ;
  __IO uint32 cfar_acc_sum_l ;
  __IO uint32 cfar_ord_idx ;
  __IO uint32 cfar_ord_value ;
  __IO uint32 siggen_step ;
  __IO uint32 siggen_ctrl ;
  __IO uint32 agc_gain_tb_ch0_0 ;
  __IO uint32 agc_gain_tb_ch0_1 ;
  __IO uint32 agc_gain_tb_ch0_2 ;
  __IO uint32 agc_gain_tb_ch0_3 ;
  __IO uint32 agc_gain_tb_ch0_4 ;
  __IO uint32 agc_gain_tb_ch0_5 ;
  __IO uint32 agc_gain_tb_ch0_6 ;
  __IO uint32 agc_gain_tb_ch0_7 ;
  __IO uint32 agc_gain_tb_ch0_8 ;
  __IO uint32 agc_gain_tb_ch0_9 ;
  __IO uint32 agc_gain_tb_ch0_10 ;
  __IO uint32 agc_gain_tb_ch0_11 ;
  __IO uint32 agc_gain_tb_ch0_12 ;
  __IO uint32 agc_gain_tb_ch0_13 ;
  __IO uint32 agc_gain_tb_ch0_14 ;
  __IO uint32 agc_gain_tb_ch0_15 ;
  __IO uint32 agc_gain_tb_ch0_16 ;
  __IO uint32 agc_gain_tb_ch0_17 ;
  __IO uint32 agc_gain_tb_ch0_18 ;
  __IO uint32 agc_gain_tb_ch0_19 ;
  __IO uint32 agc_gain_tb_ch0_20 ;
  __IO uint32 agc_gain_tb_ch0_21 ;
  __IO uint32 agc_gain_tb_ch0_22 ;
  __IO uint32 agc_gain_tb_ch0_23 ;
  __IO uint32 agc_gain_tb_ch0_24 ;
  __IO uint32 agc_gain_tb_ch0_25 ;
  __IO uint32 agc_gain_tb_ch0_26 ;
  __IO uint32 agc_gain_tb_ch0_27 ;
  __IO uint32 agc_gain_tb_ch0_28 ;
  __IO uint32 agc_gain_tb_ch0_29 ;
  __IO uint32 agc_gain_tb_ch0_30 ;
  __IO uint32 agc_gain_tb_ch0_31 ;
  __IO uint32 agc_gain_tb_ch0_32 ;
  __IO uint32 agc_gain_tb_ch0_33 ;
  __IO uint32 agc_gain_tb_ch0_34 ;
  __IO uint32 agc_gain_tb_ch0_35 ;
  __IO uint32 agc_gain_tb_ch0_36 ;
  __IO uint32 agc_gain_tb_ch0_37 ;
  __IO uint32 agc_gain_tb_ch0_38 ;
  __IO uint32 agc_gain_tb_ch0_39 ;
  __IO uint32 agc_gain_tb_ch0_40 ;
  __IO uint32 agc_gain_tb_ch0_41 ;
  __IO uint32 agc_gain_tb_ch0_42 ;
  __IO uint32 agc_gain_tb_ch0_43 ;
  __IO uint32 agc_gain_tb_ch0_44 ;
  __IO uint32 agc_gain_tb_ch0_45 ;
  __IO uint32 agc_gain_tb_ch0_46 ;
  __IO uint32 agc_gain_tb_ch0_47 ;
  __IO uint32 agc_lna_gain_tb_ch0_0 ;
  __IO uint32 agc_lna_gain_tb_ch0_1 ;
  __IO uint32 agc_lna_gain_tb_ch0_2 ;
  __IO uint32 agc_lna_gain_tb_ch0_3 ;
  __IO uint32 agc_lna_gain_tb_ch0_4 ;
  __IO uint32 agc_lna_gain_tb_ch0_5 ;
  __IO uint32 agc_lna_gain_tb_ch0_6 ;
  __IO uint32 agc_lna_gain_tb_ch0_7 ;
  __IO uint32 agc_gain_tb_ch1_0 ;
  __IO uint32 agc_gain_tb_ch1_1 ;
  __IO uint32 agc_gain_tb_ch1_2 ;
  __IO uint32 agc_gain_tb_ch1_3 ;
  __IO uint32 agc_gain_tb_ch1_4 ;
  __IO uint32 agc_gain_tb_ch1_5 ;
  __IO uint32 agc_gain_tb_ch1_6 ;
  __IO uint32 agc_gain_tb_ch1_7 ;
  __IO uint32 agc_gain_tb_ch1_8 ;
  __IO uint32 agc_gain_tb_ch1_9 ;
  __IO uint32 agc_gain_tb_ch1_10 ;
  __IO uint32 agc_gain_tb_ch1_11 ;
  __IO uint32 agc_gain_tb_ch1_12 ;
  __IO uint32 agc_gain_tb_ch1_13 ;
  __IO uint32 agc_gain_tb_ch1_14 ;
  __IO uint32 agc_gain_tb_ch1_15 ;
  __IO uint32 agc_gain_tb_ch1_16 ;
  __IO uint32 agc_gain_tb_ch1_17 ;
  __IO uint32 agc_gain_tb_ch1_18 ;
  __IO uint32 agc_gain_tb_ch1_19 ;
  __IO uint32 agc_gain_tb_ch1_20 ;
  __IO uint32 agc_gain_tb_ch1_21 ;
  __IO uint32 agc_gain_tb_ch1_22 ;
  __IO uint32 agc_gain_tb_ch1_23 ;
  __IO uint32 agc_gain_tb_ch1_24 ;
  __IO uint32 agc_gain_tb_ch1_25 ;
  __IO uint32 agc_gain_tb_ch1_26 ;
  __IO uint32 agc_gain_tb_ch1_27 ;
  __IO uint32 agc_gain_tb_ch1_28 ;
  __IO uint32 agc_gain_tb_ch1_29 ;
  __IO uint32 agc_gain_tb_ch1_30 ;
  __IO uint32 agc_gain_tb_ch1_31 ;
  __IO uint32 agc_gain_tb_ch1_32 ;
  __IO uint32 agc_gain_tb_ch1_33 ;
  __IO uint32 agc_gain_tb_ch1_34 ;
  __IO uint32 agc_gain_tb_ch1_35 ;
  __IO uint32 agc_gain_tb_ch1_36 ;
  __IO uint32 agc_gain_tb_ch1_37 ;
  __IO uint32 agc_gain_tb_ch1_38 ;
  __IO uint32 agc_gain_tb_ch1_39 ;
  __IO uint32 agc_gain_tb_ch1_40 ;
  __IO uint32 agc_gain_tb_ch1_41 ;
  __IO uint32 agc_gain_tb_ch1_42 ;
  __IO uint32 agc_gain_tb_ch1_43 ;
  __IO uint32 agc_gain_tb_ch1_44 ;
  __IO uint32 agc_gain_tb_ch1_45 ;
  __IO uint32 agc_gain_tb_ch1_46 ;
  __IO uint32 agc_gain_tb_ch1_47 ;
  __IO uint32 agc_lna_gain_tb_ch1_0 ;
  __IO uint32 agc_lna_gain_tb_ch1_1 ;
  __IO uint32 agc_lna_gain_tb_ch1_2 ;
  __IO uint32 agc_lna_gain_tb_ch1_3 ;
  __IO uint32 agc_lna_gain_tb_ch1_4 ;
  __IO uint32 agc_lna_gain_tb_ch1_5 ;
  __IO uint32 agc_lna_gain_tb_ch1_6 ;
  __IO uint32 agc_lna_gain_tb_ch1_7 ;
}DSP_TypeDef;
#endif
